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ad7994/ad7993 a rev. prf 09/03 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: ht tp://www.analog.com fax: 781/326-8703 analog devices, inc., 2003 4-channel, 12-/10-bit adcs with i 2 c compatible interface in 16-lead tssop preliminary technical data preliminary technical data functional block diagram features 12-bit adc with fast conversion time: 2 s four single-ended analog input channels specified for v dd of 2.7 v to 5.5 v low power consumption fast throughput rate:- 188 ksps sequencer operation automatic cycle mode i 2 c r compatible serial interface i 2 c r interface supports: standard, fast, and high-speed modes out of range indicator/alert function pin-selectable addressing via as two versions allow five i 2 c addresses shutdown mode: 1 a max 16-lead tssop package general description the ad7994/ad7993 are 4 channel, 12-/10-bit, high speed, low power, successive-approximation adcs re- spectively. they operate from a single 2.7 v to 5.5 v power supply and feature a conversion time of 2 s. the parts contain a four channel multiplexer and track/hold amplifier which can handle input frequencies in excess of tbd khz. the ad7994/ad7993 provide a two-wire serial interface which is compatible with i 2 c interfaces. the parts come in two versions, ad7994-0/ad7993-0 to ad7994-1/ ad7993-1. each version allows for a minimum of two different i 2 c addresses. the i 2 c interface on the ad7994- 0/ad7993-0 supports standard and fast i 2 c interface modes. the i 2 c interface on the ad7994-1/ad7993-1 supports standard, fast and two high-speed i 2 c interface modes. the ad7994/ad7993 normally remain in a shutdown state while not converting, powering up only for conver- sions. the conversion process can be controlled using the convst pin, an automatic conversion cycle selected through software control, or a mode where conversions occur across write operations. there are no pipeline de- lays associated with the part. the reference for the part is applied externally to the ref in pin and can be in the range of 1.2v to v dd. this allows the widest dynamic input range to the adc. product highlights 1. 2 s conversion time with low power consumption. 2. i 2 c compatible serial interface with pin selectable addresses. two ad7994/ad7993 versions allow five ad7994/ad7993 devices to be connected to the same serial bus. 3 . the parts feature automatic shutdown while not convert- ing to maximize power efficiency. current consumption is 1 a max when in shutdown. 4. reference can be driven up to the power supply. 5. out of range indicator which can be software disabled/ enabled. 6. oneshot and automatic conversion rates. 7. no pipeline delay the part features a standard successive-approximation adc. smbus is a trademark and i 2 c is a registered trademark of philips corporation t/h v in 1 12-/10-bit successive approximation adc control logic i/p mux v in 2 ad7994/ad7993 v dd scl i 2 c interface conversion result register configuration register cycle timer register alert status register sda gnd alert gnd as oscillator ref in v in 3 v in 4 data low limit register ch1-ch4 data high limit register ch1-ch4 hysteresis register ch1-ch4 on-chip registers can be programmed with high and low limits for the conversion result, and an open drain out of range indicator output (alert), becomes active when the programmed high or low limits are violated by the conversion result. this output can be used as an interrupt.
?2? rev. prf preliminary technical data ( v dd = +2.7 v to +5.5 v, unless otherwise noted ; ref in = 2.5 v; f scl = 3.4 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter b version 1 units test conditions/comments dynamic performance f in = 10khz sine wave signal to noise + distortion (sinad) 2 70 db min signal to noise ratio (snr) 2 71 db min total harmonic distortion (thd) 2 -78 db typ peak harmonic or spurious noise (sfdr) 2 -80 db typ intermodulation distortion (imd) 2 fa = tbd khz, fb = tbd khz second order terms -78 db typ third order terms -78 db typ aperture delay 10 ns max aperture jitter 10 ps typ channel-to-channel isolation tbd db typ f in = tbd khz full power bandwidth t b d khz typ @ 3 db tbd khz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max 0.6 lsb typ differential nonlinearity 2 +1.5/-0.9 lsb max guaranteed no missed codes to 12 0.75 lsb typ b its. offset error 2 1.5 lsb max offset error match 2 0.5 lsb max gain error 2 1.5 lsb max gain error match 2 0.5 lsb max analog input input voltage ranges 0 to ref in volts dc leakage current 1 a max input capacitance 30 pf typ reference input ref in input voltage range 1.2 to v dd v min/vmax dc leakage current 1 a max input capacitance t b d pf max input impedance t b d k typ logic inputs (sda, scl) input high voltage, v inh 0.7(v dd ) v min input low voltage, v inl 0.3(v dd ) v max input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 2,3 10 pf max input hysteresis, v hyst t b d v min logic input ( convst ) input high voltage, v inh 2.4 v min v dd = 5v 2.0 v min v dd = 3 v input low voltage, v inl 0.8 v max v dd = 5v 0.4 v max v dd = 3v input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 2,3 10 pf max logic outputs (open drain) output low voltage, v ol 0.4 v max i sink = 3ma 0.6 v max i sink = 6ma floating-state leakage current 1 a max floating-state output capacitance 2,3 tbd pf max output coding straight (natural) binary . ad7994?specifications 1
?3? rev. prf preliminary technical data ( v dd = +2.7 v to +5.5 v, unless otherwise noted ; ref in = 2.5 v; f scl = 3.4 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter b version 1 units test conditions/comments conversion rate see interface section conversion time 2 s typ track/hold acquisition time tbd ns max full-scale step input t b d ns max sine wave input <= 30 khz throughput rate 3.4 ksps max standard mode scl = 100 khz 13 ksps max fast mode scl = 400 khz 79 ksps max high-speed mode scl = 3.4 mhz power requirements v dd 2.7/5.5 v min/max i dd digital inputs = 0 v or v dd peak current t b d a max peak current during conversion power down mode , interface inactive 0.2/0.6 a max v dd = 3 v/5 v. interface active 0.05/0.2 ma max v dd = 3 v/5 v 400 khz scl. 0.3/0.8 ma max v dd = 3 v/5 v 3.4 mhz scl. operating, interface inactive 0.06/0.15 ma max v dd = 3 v/5 v 400 khz scl. 0.3/0.6 ma max v dd = 3 v/5 v 3.4 mhz scl. interface active 0.15/0.35 ma max v dd = 3 v/5 v 400 khz scl. 0.6/1.4 ma max v dd = 3 v/5 v 3.4 mhz scl. notes 1 temperature ranges as follows: b version: ?40c to +85c. 2 see terminology. 3 sample tested @ +25c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice. ad7994?specifications 1
?4? rev. prf preliminary technical data ( v dd = +2.7 v to +5.5 v, unless otherwise noted ; ref in = 2.5 v; f scl = 3.4 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter b version 1 units test conditions/comments dynamic performance f in = 10khz sine wave signal to noise + distortion (sinad) 2 61 db min signal to noise ratio (snr) 2 tbd db min total harmonic distortion (thd) 2 -73 db typ peak harmonic or spurious noise (sfdr) 2 -74 db typ intermodulation distortion (imd) 2 fa = tbd khz, fb = tbd khz second order terms -78 db typ third order terms -78 db typ aperture delay 10 ns max aperture jitter 10 ps typ channel-to-channel isolation tbd db typ f in = tbd khz full power bandwidth tbd khz typ @ 3 db tbd khz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 2 1 lsb max 0.6 lsb typ differential nonlinearity 2 0.9 lsb max guaranteed no missed codes to 10 bits. offset error 2 1 lsb max offset error match 2 0.5 lsb max gain error 2 1 lsb max gain error match 2 0.5 lsb max total unadjusted error (tue) 2 1 lsb max analog input input voltage ranges 0 to ref in volts dc leakage current 1 a max input capacitance 30 pf typ reference input ref in input voltage range tbd/tbd v m in/vmax dc leakage current 1 a max input capacitance t b d pf max input impedance t b d k typ logic inputs (sda, scl, convst ) input high voltage, v inh 0.7(v dd ) v min input low voltage, v inl 0.3(v dd ) v max input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 2,3 10 pf max input hysteresis, v hyst t b d v min logic input ( convst ) input high voltage, v inh 2.4 v min v dd = 5v 2.0 v min v dd = 3 v input low voltage, v inl 0.8 v max v dd = 5v 0.4 v max v dd = 3v input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 2,3 10 pf max logic outputs (open drain) output low voltage, v ol 0.4 v max i sink = 3ma 0.6 v max i sink = 6ma floating-state leakage current 1 a max floating-state output capacitance 2,3 tbd pf max output coding straight (natural) binary . ad7993?specifications 1
?5? rev. prf preliminary technical data ( v dd = +2.7 v to +5.5 v, unless otherwise noted ; ref in = 2.5 v; f scl = 3.4 mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) p s s p t 6 t 4 t 1 t 3 t 5 t 8 t 2 t 11 t 12 t 6 scl sda t 7 t 9 t 10 s = start condition p = stop condition i 2 c timing specifications 1 ( v dd = +2.7 v to +5.5 v, unless otherwise noted ; ref in = 2.5 v; unless otherwise noted; t a = t min to t max , unless otherwise noted..) ad7994/ad7993 limit at t min , t max parameter conditions min max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz high-speed mode, c b = 100pf max 3.4 m h z high-speed mode, c b = 400pf max 1.7 m h z t 1 standard mode 4 st high , scl high time fast mode 0.6 s high-speed mode, c b = 100pf max 6 0 ns high-speed mode, c b = 400pf max 120 ns t 2 standard mode 4.7 st low , scl low time fast mode 1.3 s high-speed mode, c b = 100pf max 160 ns high-speed mode, c b = 400pf max 320 ns t 3 standard mode 250 - ns t su;dat , data setup time fast mode 100 - ns high-speed mode 10 - ns ad7993?specifications 1 notes 1 temperature ranges as follows: b version: ?40c to +85c. 2 see terminology. 3 sample tested @ +25c to ensure compliance. 4 see power versus throughput rate section. specifications subject to change without notice. figure 1. two-wire serial interface timing diagram parameter b version 1 units test conditions/comments conversion rate see in terface section conversion time 2 s typ track/hold acquisition time tbd ns max full-scale step input t b d ns max sine wave input <= 30 khz throughput rate 3.4 ksps max standard mode 100 khz 13 ksps max f ast mode 400 khz 79 ksps max high- speed mode 3.4 mhz power requirements v dd 2.7/5.5 v min/max i dd digital inputs = 0 v or v dd peak current t b d ma max peak current during conversion power down mode , interface inactive 0.2/0.6 a max v dd = 3 v/5 v. interface active 0.05/0.2 ma max v dd = 3 v/5 v 400 khz scl. 0.3/0.8 ma max v dd = 3 v/5 v 3.4 mhz scl. operating, interface inactive 0.06/0.15 ma max v dd = 3 v/5 v 400 khz scl. 0.3/0.6 ma max v dd = 3 v/5 v 3.4 mhz scl. interface active 0.15/0.35 ma max v dd = 3 v/5 v 400 khz scl. 0.6/1.4 ma max v dd = 3 v/5 v 3.4 mhz scl.
ad7994/ad7993 ?6? rev. prf preliminary technical data ad7994/ad7993 limit at t min , t max parameter conditions min max unit description t 4 standard mode 0 3.45 st hd;dat , data hold time fast mode 0 0.9 s high-speed mode, c b = 100pf max 0 7 0 ns high-speed mode, c b = 400pf max 0 150 ns t 5 standard mode 4.7 st su;sta , set-up time for a repeated start fast mode 0.6 s condition high-speed mode 160 ns t 6 standard mode 4 st hd;sta , hold time (repeated) start fast mode 0.6 s condition high-speed mode 160 ns t 7 standard mode 4.7 st buf , bus free time between a stop and a fast mode 1.3 s start condition. t 8 standard mode 4 st su;sto , set-up time for stop condition fast mode 0.6 s high-speed mode 160 ns t 9 standard mode - 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 1 0 8 0 ns high-speed mode, c b = 400pf max 2 0 160 ns t 10 standard mode - 300 ns t fda , fall time of sda signal fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 1 0 8 0 ns high-speed mode, c b = 400pf max 2 0 160 ns t 11 standard mode - 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 1 0 4 0 ns high-speed mode, c b = 400pf max 2 0 8 0 ns t 11a standard mode - 1000 ns t rcl1 , rise time of scl signal after a re- fast mode 20 + 0.1c b 300 ns peated start condition and after an high-speed mode, c b = 100pf max 1 0 8 0 ns acknowledge bit. high-speed mode, c b = 400pf max 2 0 160 ns t 12 standard mode - 300 ns t fcl , fall time of scl signal fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 1 0 4 0 ns high-speed mode, c b = 400pf max 2 0 8 0 ns t sp 4 fast mode 0 50 ns pulsewidth of spike suppressed. high-speed mode 0 10 ns t power-up 1 s power-up time i 2 c timing specifications 1 ( continued.) notes 1 see figure 1. c b refers to the capacitance load on the bus line. hs-mode timing specifications apply to the ad7994-1/ad7993-1 only. stan- dard and fast mode timing specifications apply to both the ad7994-0/ad7993-0 and the ad7994-1/ad7993-1. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate b ut has a nega- tive effect on emc behavior of the part. 4 input filtering on both the scl and sda inputs suppress noise spikes that are less than 50ns or 10ns for fast mode or high-spee d mode respectivley. specifications subject to change without notice.
ad7994/ad7993 ?7? rev. prf preliminary technical data caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7994/ad7993 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of func- tionality. ordering guide model 1 temperature range linearity error 2 (max) p ackage option 3 ad7994bru-0 -40c to +85c 1 lsb ru-16 AD7994BRU-1 -40c to +85c 1 lsb ru-16 ad7993bru-0 -40c to +85c 1 lsb ru-16 ad7993bru-1 -40c to +85c 1 lsb ru-16 absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd ?0.3 v to 7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd -0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to 7 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 2 10 ma operating temperature range commercial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature +150c 16-ld tssop package ja thermal impedance 150.4c/w (tssop) jc thermal impedance 27.6c/w (tssop) lead temperature, soldering vapor phase (60 secs) +215c infared (15 secs) +220c notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. notes 1 the ad7994-0/ad7993-0 supports standard and fast i 2 c interface modes. the ad7994-1/ad7993-1 supports standard, fast and highspeed i 2 c interface modes. 2 linearity error here refers to integral nonlinearity 3 ru = tssop.
ad7994/ad7993 ?8? rev. prf preliminary technical data pin function description pin mnemonic function agnd analog ground. ground reference point for all circuitry on the ad7994/ad7993. all analog input signals should be referred to this gnd voltage. v dd power supply input. the v dd range for the ad7994/ad7993 is from +2.7v to +5.5v. ref in voltage reference input. the external reference for the ad7994/ad7993 should 0.1 f capacitor should be placed between the ref in pin and agnd. v in 1 analog input 1. single-ended analog input channel. the input range is 0v to ref in . v in 3 analog input 3. single-ended analog input channel. the input range is 0v to ref in . v in 4 analog input 4. single-ended analog input channel. the input range is 0v to ref in . v in 2 analog input 2. single-ended analog input channel. the input range is 0v to ref in . a s logic input. address select input which selects one of three i 2 c addresses for the ad7994/ ad7993 as shown in table i. convst logic input signal. convert start signal. this is an edge triggered logic input. the rising edge of this signal powers up the part. the power up time for the part is 1 s. the falling edge of convst places the track/hold into hold mode and initiates a conversion. a power up time of at least 1 s must be allowed for the convst high pulse, otherwise the conver- sion result will be invalid. (see modes of operation section) alert/busy digital output, selectable as an alert or busy output function. when configured as an alert output, this pin acts as an out of range indicator, and if enabled becomes active when the conversion result violates the data high or data low values. see limit registers section. when configured as a busy output, this pin becomes active when a conversion is in progress. sda digital i/o. serial bus bi-directional data. open-drain output. external pull-up resistor required. scl digital input. serial bus clock. external pull-up resistor required. ad7994/ad7993 pin configuration tssop ad7994 top view 1 2 3 4 13 14 15 16 sda scl v dd agnd v in4 5 (not to scale) alert 12 agnd 11 as 10 9 agnd ref in 6 v in1 7 v in3 8 agnd agnd v in2
ad7994/ad7993 ?9? rev. prf preliminary technical data table i. i 2 c address selection part number as pin i 2 c address ad7993-0 gnd 010 0001 ad7993-0 v dd 010 0010 ad7993-1 gnd 010 0011 ad7993-1 v dd 010 0100 ad7993-x 1 float 010 0000 note:- 1. if the as pin is left floating on any of the ad7993 parts the device address will be 010 0000 part number as pin i 2 c address ad7994-0 gnd 010 0001 ad7994-0 v dd 010 0010 ad7994-1 gnd 010 0011 ad7994-1 v dd 010 0100 ad7994-x 1 float 010 0000 note :- 1. if the as pin is left floating on any of the ad7994 parts the device address will be 010 0000
ad7994/ad7993 ?10? rev. prf preliminary technical data channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a fullscale tbd khz sine wave signal to the nonselected input channels and determining how much the tbd khz signal is attenuated in the selected channel. this figure is given worse case across all channels. aperture delay this is the measured interval between the leading edge of the sampling clock and the point at which the adc actu- ally takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the sample is taken. full power bandwidth the full power bandwidth of an adc is that input fre- quency at which the amplitude of the reconstructed fun- damental is reduced by 0.1 db or 3 db for a full-scale input psrr (power supply rejection) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200 mv p-p sine wave applied to the adc v dd supply of frequency f s . psrr (db) = 10 log (pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs coupled into the adc v dd sup- ply. integral nonlinearity this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e agnd + 1lsb offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., ref in ? 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two chan- nels. terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the num- ber of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theo- retical signal to (noise + distortion) ratio for an ideal n- bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7994/ ad7993, it is defined as: thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest har- monic in the spectrum, but for adcs where the har- monics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequen- cies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7994/ad7993 is tested using the ccif stan- dard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are speci- fied separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the funda- mentals expressed in dbs.
ad7994/ad7993 ?11? rev. prf preliminary technical data ad7994/ad7993 typical performance curves tpc 1 shows a typical fft plot for the ad7994 at tbd ksps sample rate and tbd khz input frequency. tpc 1. ad7994 dynamic perfor- mance at tbd ksps. tpc 2. ad7993 dynamic perfor- mance at tbd ksps. tpc 3. psrr vs supply ripple fre- quency. tpc 4. ad7994 sinad vs analog input frequency for various sup- ply voltages at tbd ksps. tpc 5. ad7994 typical inl v dd = 5v. tpc 6. ad7994 typical dnl v dd = 5v. tpc 7. ad7994 typical inl v dd = 3v. tpc 8. ad7994 typical dnl v dd = 3v. tpc 9. ad7994 change in inlvs reference voltage v dd = 5v.
ad7994/ad7993 ?12? rev. prf preliminary technical data tpc 10. ad7994 change in dnl vs reference voltage. tpc 11. ad7994 shutdown cur- rent vs supply voltage, -40 , 25 and 85 c. tpc 12. ad7994 supply current vs i 2 c bus rate for v dd = 3v and 5v. tpc 13. ad7994 supply current vs supply voltage for various temperatures. tpc 14. ad7994 enob vs refer- ence voltage, v dd = 3v and v dd = 5v.
ad7994/ad7993 ?13? rev. prf preliminary technical data circuit information the ad7994/ad7993 are fast, low-power, 12-/10-bit, single supply, 4 channel a/d converters respectively. the parts can be operated from a 2.7 v to 5.5 v supply. the ad7994/ad7993 provide the user with a 4-channel multiplexer, an on-chip track/hold, a/d converter, an on- chip oscillator, internal data registers and an i 2 c compat- ible serial interface, all housed in a 16-lead tssop package, which offers the user considerable space saving advantages over alternative solutions. an external reference is required by the ad7994/ad7993, and this reference can be in the range of 1.2 v to v dd . the ad7994/ad7993 will normally remain in a power- down state while not converting. when supplies are first applied the part will come up in a shutdown state. power- up is intitiated prior to a conversion and the device returns to power-down upon completion of the conversion. con- versions can be initiated on the ad7994/ad7993 by either pulsing the convst signal, using an automatic cycling mode or using a mode where wake-up and conversion oc- cur during the write function ( see modes of operation section). on completion of a conversion the ad7994/ ad7993 will enter shutdown mode again. this automatic shutdown feature allows power saving between conversions. this means any read or write operations across the i 2 c interface can occur while the device is in shut-down. adc transfer function the output coding of the ad7994/ad7993 is straight binary. the designed code transitions occur at successive integer lsb values (i.e., 1lsb, 2lsbs, etc.). the lsb size for the ad7994 is = ref in /4096 and ref in /256 for the ad7993 . the ideal transfer characteristic for the ad7994/ad7993 is shown in figure 4 below. converter operation the ad7994/ad7993 are successive approximation ana- log-to-digital converters based around a capacitive dac. figures 2 and 3 show simplified schematics of the adc during its acquisition and conversion phase respectively. figure 2 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in x. when the adc starts a conversion, see figure 3, sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the input is discon- nected once the conversion begins. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced the conversion is com- plete. the control logic generates the adc output code. figure 4 shows the adc transfer function. figure 2. adc acquisition phase figure 3. adc conversion phase figure 4. ad7994/ad7993 transfer characteristic typical connection diagram figure 5 shows the typical connection diagram for the ad7994/ad7993. in figure 5 the address select pin, as, is tied to v dd , however as can also be either tied to gnd or left floating, allowing the user to select up to three ad7994/ad7993 devices on the same serial bus. an external reference must be applied to the ad7994/ ad7993. this reference can be in the range of 1.2 v to v dd . a precision reference like the ref 19x family, adr421, adr03, adr381 can be used to supply the reference voltage to the adc. sda and scl form the two-wire i 2 c/smbus compatible interface. external pull-up resistors should be added to the sda and scl bus lines. the ad7994-0/ad7993-0 support standard and fast i 2 c interface modes. while the ad7994-1/ad7993-1 support standard, fast and high-speed i 2 c interface modes. therefore if operating the ad7994/ad7993 in either standard or fast mode, up to five ad7994/ad7993 de- vices (3 x ad7994-0/ad7993-0 and 2 x ad7994-1/ ad7993-1 or 3 x ad7994-1/ad7993-1 and 2 x ad7994- 0/ad7993-0) can be connected to the bus. when operat- ing in hs-mode then up to three ad7994-1/ad7993-1 devices can be connected to the bus. wake-up from power-down prior to a conversion is ap- proximately 1s while conversion time is approximately 2s. the ad7994/ad7993 enters power-down mode again after each conversion, this will be useful in applica- tions where power consumption is of concern. capacitive dac v in comparator control logic sw1 a b sw2 agnd capacitive dac v in comparator control logic sw1 a b sw2 agnd 000...000 adc code analog input 0 v to ref in 111...111 000...001 000...010 111...110 111...000 011...111 agnd +1 lsb +ref in -1lsb ad7994 1 lsb = ref in /4096 ad7993 1 lsb = ref in /256
ad7994/ad7993 ?14? rev. prf preliminary technical data analog input figure 6 shows an equivalent circuit of the analog input sturcture of the ad7994/ad7993. the two diodes d1 and d2 provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 10 ma is the maxi- mum current these diodes can conduct without causing irreversable damage to the part. the capacitor c1 in figure 6 is typically about 4pf and can primarily be attributed to pin capacitance. the resis- tor r1 is a lumped component made up of the on resis- tance (r on ) of a switch(track and hold switch) and also includes the r on of the input multiplexer. the total resis- tance is typically about 400 ? ? ?
ad7994/ad7993 ?15? rev. prf preliminary technical data internal register structure the ad7994/ad7993 contains seventeen internal regis- ters, as shown in figure 9, that are used to store conver- sion results, high and low conversion limits, and to configure and control the device. sixteen are data registers and one is an address pointer register. figure 9. ad7994/ad7993 register structure each data register has an address which is pointed to by the address pointer register when communicating with it. the conversion result register is the only data register that is read only. table ii. address pointer register c4 c3 c2 c1 p3 p2 p1 p0 0000 r egister select address pointer register the address pointer register itself does not have, nor does it require, an address, as it is the register to which the first data byte of every write operation is written automatically. the address pointer register is an 8-bit register in which the four lsbs are used as pointer bits to store an address that points to one of the data registers of the ad7994/ ad7993, while the four msbs are used as command bits when operating in mode 2 (see modes of operation sec- tion). the first byte following each write address is the address of one of the data registers, which is stored in the address pointer register, and selects the data register to which subsequent data bytes are written. only the four lsbs of this register are used to select a data register. on power up the address point register contains all 0?s, pointing to the conversion result register. configuration register address pointer register serial bus interface sda scl d a t a data low register ch2 data high register ch2 data low register ch1 hysteresis register ch1 data high register ch1 cycle timer register alert status register conversion result register hysteresis register ch2 data high register ch3 data low register ch3 hysteresis register ch3 data high register ch4 data low register ch4 hysteresis register ch4 table iii. ad7994/ad7993 register addresses p3 p2 p1 p0 registers 0 0 0 0 conversion result register (read) 0 0 0 1 alert status register (read/write) 0 0 1 0 configuration register (read/write) 0 0 1 1 cycle timer register (read/write) 0 1 0 0 data low reg ch1 (read/write) 0 1 0 1 data high reg ch1 (read/write) 0 1 1 0 hysteresis reg ch1 (read/write) 0 1 1 1 data low reg ch2 (read/write) 1 0 0 0 data high reg ch2 (read/write) 1 0 0 1 hysteresis reg ch2 (read/write) 1 0 1 0 data low reg ch3 (read/write) 1 0 1 1 data high reg ch3 (read/write) 1 1 0 0 hysteresis reg ch3 (read/write) 1 1 0 1 data low reg ch4 (read/write) 1 1 1 0 data high reg ch4 (read/write) 1 1 1 1 hysteresis reg ch4 (read/write)
ad7994/ad7993 ?16? rev. prf preliminary technical data bit mnemonic comment d7-d4 ch4-ch1 these four channel address bits select the analog input channel(s) to be converted on. a 1 in any of bits d7 to d4 selects a channel for conversion. if more than one channel bit is set to 1 then the ad7994/ad7993 will sequence through the selected channels, starting with the lowest channel. all unused channels should be set to zero. table v shows how these four channel address bits are decoded. prior to initiating a conversion a channel(s) must be selected in the configuration register. d 3 fltr the value written to this bit of the control register determines whether the filtering on sda and scl is enabled or to be bypassed. if this bit is a 1 then the the filtering is enabled, if it is a 0, then the filtering is bypassed. d2 alert en the hardware alert function is enabled if this bit is set to 1 and disabled if set to 0. this bit is used in conjunction with the busy/alert bit to determine if the alert/busy pin will act as an alert or a busy output. (see table vi.) d1 busy/alert this bit is used in conjunction with the alert en bit to determine if the alert/busy output, pin 13, will act as an alert or busy output (see table v1), or if pin 13 is configured as an alert output pin, if it is to be reset. when reading the configuration registerd1 will always be a 0 when d2 is a 1. d0 busy/alert this bit determines the active polarity of the alert/busy pin regardless of whether it is polarity configured as an alert or busy output. it is active low if this bit is set to 0, and it is active high if set to 1. configuration register the configuration register is an 8-bit read/write register that is used to set the operating modes of the ad7994/ ad7993. the bit functions of all 8 bits of the configuration register are outlined in table iv. table iv. configuration register bit function description d7 d6 d5 d4 d3 d2 d1 d0 ch4 ch3 ch2 ch1 fltr alert en busy/alert alert/busy polarity 0* 0* 0* 0* 1* 0* 0* 0* *default settings at power-up
ad7994/ad7993 ?17? rev. prf preliminary technical data conversion result register the conversion result register is a 16-bit read-only reg- ister which stores the conversion result from the adc in straight binary format. a two byte read is necessary to read data from this register. table viia shows the contents of the first byte to be read while table viib show the contents of the second byte to be read from ad7994/ ad7993. the ad7994/ad7993 conversion result consists of an alert_flag bit, a leading zero, two channel identifier bits and the 12-/10- bit data result. for the ad7993 the two lsbs (d1 and d0) of the second read will contain two zeros. the alert_flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. the master may wish to read the alert status register to obtain more informa- tion on where the alert occurred if this alert_flag bit is set. this is followed by a leading zero and the two channel indentifier bits indicating which channel the conversion result corresponds to. the 12-/10-bit conversion result then follows msb first. table vi. alert/busy function d2 d1 alert/busy pin configuration 0 0 pin does not provide any interrupt signal. 0 1 pin configured as a busy output. 1 0 pin configured as an alert output. 1 1 resets alert output pin, alert_flag bit in conversion result reg, and entire alert status reg ( if any active). note 1:- the ad7994/ad7994 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence. table v. channel selection d7 d6 d5 d4 analog input channel 0 0 0 0 no channel selected, see address pointer byte, mode 2 0 0 0 1 convert on v in 1 0 0 1 0 convert on v in 2 0 0 1 1 sequence between v in 1 and v in 2 0 1 0 0 convert on v in 3 0 1 0 1 sequence between v in 1 and v in 3 0 1 1 0 sequence between v in 2 and v in 3 0 1 1 1 sequence between v in 1, v in 2 and v in 3 1 0 0 0 convert on v in 4 1 0 0 1 sequence between v in 1 and v in 4 1 0 1 0 sequence between v in 2 and v in 4 1 0 1 1 sequence between v in 1, v in 2 and v in 4 1 1 0 0 sequence between v in 3 and v in 4 1 1 0 1 sequence between v in 1, v in 3 and v in 4 1 1 1 0 sequence between v in 2, v in 3 and v in 4 1 1 1 1 sequence between v in 1, v in 2, v in 3 and v in 4 alert_flag 1 zero ch id1 ch id0 channel# result 0/1 0 0 0 channel 1(v in 1) 0/1 0 0 1 channel 2(v in 2) 0/1 0 1 0 channel 3(v in 3) 0/1 0 1 1 channel 4(v in 4) table viib. conversion value register (second read) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1/0 b0/0 table viia. conversion value register (first read) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag zero ch id1 ch id0 msb b10 b9 b8 if 1/1 is written to bits d2/d1 in the configuration regis- ter to reset the alert pin, the alert flag bit and the alert status register; the contents of the configuration register will read 1/0 for d2/d1 respectively if read back.
ad7994/ad7993 ?18? rev. prf preliminary technical data limit registers the ad7994/ad7993 has four pairs of limit registers, each to store high and low conversion limits for each ana- log input channel. each pair of limit registers has one associated hysteresis register. all twelve registers are 16- bits wide, only the 12 lsbs of the registers are used for the ad7994/ad7993, however on the ad7993 the 2 lsbs, d1 and d0, should contain 0s. on power-up, the contents of the data high register for each channel will be fullscale, while the contents of the data low registers will be zeroscale by default. the limit registers can be used to monitor the conversion results on each on the analog input channels. the ad7994/ad7993 will signal an alert ( in either hardware or software or both depend- ing on configuration) if the result moves outside the upper or lower limit set by the limit registers. data high register ch1/ch2/ch3/ch4 the data high register for each channel is a 16-bit read/ write register, only the 12 lsbs of the register are used. the registers store the upper limit that will activate the alert output and/or the alert_flag bit in the conver- sion result register. therefore, if the value in the con- version result register is greater than the value in the data high register, then the alert_flag bit is set to 1 and the alert pin is activated (the latter is true if alert is enabled in the configuration register). when the conversion result returns to a value at least n lsbs below the data high register value the alert output pin and alert_flag bit will be reset. the value of n is taken from the 12-bit hysteresis register associated with that channel. the alert pin can also be reset by writ- ing to bits d2, d1 in the configuration register. for the ad7993, d1 and d0 of the data high register should contain 0?s. table viiia. data high register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag 0 0 0 b11 b10 b9 b8 table viiib. data high register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 data low register ch1/ch2/ch3/ch4 the data low register for each channel is a 16-bit read/ write register, of which only the 12 lsbs are used. the register stores the lower limit that will activate the alert output and/or the alert_flag bit in the conver- sion result register. therefore, if the value in the conver- sion result register is less than the value in the data low register, then the alert_flag bit is set to 1 and the alert pin is activated (the latter is true if alert is enabled in the configuration register). when the conver- sion result returns to a value at least n lsbs above the data low register value the alert ouput pin and alert_flag bit will be reset. the value of n is taken from the 12-bit hysteresis register associated with that channel. the alert pin can also be reset by writing to bit d2,d1 in the configuration register. for the ad7993 d1 and d0 of the data low register should contain 0?s. table ixa. data low register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag 0 0 0 b11 b10 b9 b8 table ixb. data low register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 hysteresis register (ch1/ch2/ch3/ch4) each hysteresis register is a 16-bit read/write register, only the 12 lsbs of the register are used. the registers store the hysteresis value, n when using the limit registers. each pair of limit registers has a dedicated hysteresis register. the hysteresis value determines the reset point for the alert pin/alert_flag if a violation of the limits has occurred. if a hysteresis value of say 8 lsbs is re- quired on the upper and lower limits of channel 1 then the 12 bit word, 0000 0000 0000 1000, should be written to the hysteresis register ch1, the address of which is shown in table iii. on power up, the hysteresis registers will contain a value of 8 lsbs for the ad7994 and 2 lsbs for the ad7993. if a different hysteresis value is required then that value must be written to the hysteresis register for the channel in question. for the ad7993 d1 and d0 of the hysteresis register should contain 0?s. table xa. hysteresis register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag 0 0 0 b11 b10 b9 b8 table xb. hysteresis register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 using the limit registers to store min/max conversion results if fullscale, i.e. all 1s, is written to the hysteresis register for a particular channel then the data high and data low registers for that channel will no longer act as limit registers as previously described, but instead they will act as storage registers for the maximum and mini- mum conversion results returned from conversions on a channel over any given period of time. this function is useful in applications where the widest span of actual con- version results is required rather than using the alert to signal an intervention is necessary, e.g. monitoring tem- perature extremes during refrigerated goods transporta- tion. when using the limit registers to store the min and
ad7994/ad7993 ?19? rev. prf preliminary technical data table xib. alert status register bit function description bit mnemonic comment d0 ch1 lo violation of data low limit on channel 1 if this bit set to 1, no violation if 0. d1 ch1 hi violation of data high limit on chan nel 1 if this bit set to 1, no violation if 0. d2 ch2 lo violation of data low limit on channel 2 if this bit set to 1, no violation if 0. d3 ch2 hi violation of data high limit on chan nel 2 if this bit set to 1, no violation if 0. d4 ch3 lo violation of data low limit on channel 3 if this bit set to 1, no violation if 0. d5 ch3 hi violation of data high limit on chan nel 3 if this bit set to 1, no violation if 0. max conversion results, the alert_flag bit, d15, can be used to indicate that an alert has happened on another one of the input channels. it must be noted that on power-up, the contents of the data high register for each channel will be fullscale, while the contents of the data low registers will be zeroscale, by default minimum and maximum conversion values being stored in this way will be lost if power is removed or cycled. when using the limit registers to store the min and max conversion results, the alert_flag bit, d15, is used to indicate that an alert has happened on another one of the input channels. if the alert_flag bit is set to 1, it will be reset when the conversion result returns to a value at least n lsbs above the data low register value or below the data low register value or if bits d2 and d1 of the configuration register are set to 1. the alert_flag bit in the limit registers is useful if the user is not reading from the conversion result register when reading the min and max conversion results from the limit registers. alert status register the alert status register is a 8-bit read/write register, which provides information on an alert event. if a conver- sion results in activating the alert pin or the alert_flag bit in the conversion result register, as described in the limit registers section, then the alert status register may be read to gain further information. it contains 2 status bits per channel, one corresponding to the data high limit and the other to the data low limit. whichever bit has a status of 1 will show where the violation occured, i.e. on which channel and whether on upper or lower limit. if a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register then the corresponding bit for that alert event will be set also. the entire contents of the alert status register may be cleared by writing 1,1, to bits d2 and d1 in the configu- ration register as shown in table vi. this may also be acheived by ?writing? all 1?s to the alert status register itself. this means that if the alert status register is ad- dressed for a write operation which is all 1?s, then the contents of the alert status register will then be cleared or resest to all 0?s. alternatively, an individual active alert bit(s) may be reset within the alert status register by performing a write of ?1? to that bit alone. the advantage of this is that once an alert event has been serviced, that particular bit can be reset, e.g. ch1 lo , without clearing the entire contents of the alert status register, thus pre- serving the status of any additional alert, e.g. ch2 hi , which may have occured while servicing the first. if it is not necessary to clear an alert directly after servicing then obviously the alert status register may be read again im- mediately to look for any new alerts, bearing in mind that the one just serviced will still be active. table xia. alert status register d7 d6 d5 d4 d3 d2 d1 d0 ch4 hi ch4 lo ch3 hi ch3 lo ch2 hi ch2 lo ch1 hi ch1 lo d6 ch4 lo violation of data low limit on channel 4 if this bit set to 1, no violation if 0. d7 ch4 hi violation of data high limit on chan nel 4 if this bit set to 1, no violation if 0.
ad7994/ad7993 ?20? rev. prf preliminary technical data cycle timer register the cycle timer register is a 8-bit read/write register, which stores the conversion interval value for the auto- matic cycle mode of the ad7994/ad7993, see modes of operation section. the five msbs of the cycle timer register are unused and should contain 0?s at all times. on power up, the cycle timer register will contain all 0s, thus disabling the automatic cycle operation of the ad7994/ad7993. to enable the automatic cycle mode the user must write to the cycle timer register, selecting the required conversion interval. table xiia shows the structure of the cycle timer register while table xiib shows how the bits in this register are decoded to provide various automatic sampling intervals. table xiia. cycle timer register * default settings on power-up table xiib. cycle timer intervals d2 d1 d0 conversion interval (typ) 0 0 0 mode not selected 0 0 1 t convert x 32 0 1 0 t convert x 64 0 1 1 t convert x 128 1 0 0 t convert x 256 1 0 1 t convert x 512 1 1 0 t convert x 1024 1 1 1 t convert x 2048 t convert is equivalent to the conversion time of the adc. d7 d6 d5 d4 d3 d2 d1 d0 sample bit trial 0 0 0 cyc cyc cyc dealy delay bit2 bit1 bit0 0* 0* 0* 0* 0* 0* 0* 0*
ad7994/ad7993 ?21? rev. prf preliminary technical data writing to the ad7994/ad7993 depending on the register being written to, there are two different writes for the ad7994/ad7993. writing to the address pointer register for a subse- quent read in order to read from a particular register, the address pointer register must first contain the address of that reg- ister. if it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in figure 10. the write opera- tion consists of the serial bus address followed by the ad- dress pointer byte. no data is written to any of the data registers. a read operation maybe subsequently performed to read the register of interest. writing a single byte of data to the alert status regis- ter or cycle register the configuration register and cycle register are both 8-bit registers, so only one byte of data can be written to each. writing a single byte of data to one of these registers consists of the serial bus write address, the chosen data register address written to the address pointer register, followed by the data byte written to the selected data reg- ister. this is illustrated in figure 11. writing two bytes of data to a limit register, hyster- esis register or configuration register. each of the four limit registers are 12-bit registers, so two bytes of data are required to write a value to any one of them. writing two bytes of data to one of these registers consists of the serial bus write address, the chosen limit register address written to the address pointer register, followed by two data bytes written to the selected data register. this is illustrated in figure 12. serial interface control of the ad7994/ad7993 is carried out via the i 2 c-compatible serial bus. the ad7994/ad7993 is con- nected to this bus as a slave device, under the control of a master device, e.g. the processor. serial bus address like all i 2 c-compatible devices, the ad7994/ad7993 has a 7-bit serial address. the three msbs of this address for the ad7994/ad7993 are set to 010. the ad7994/ ad7993 comes in two versions, the ad7994-0/ad7993-0 and ad7994-1/ad7993-1. the two versions have three different i 2 c addresses available which are selected by either tying the address select pin, as, to gnd, to v dd or letting the pin float (see table i). by giving different addresses for the two versions, up to five ad7994/ ad7993 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the bus. see i 2 c address selection table. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda whilst the serial clock line, scl, remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (msb first) plus a r/ w bit, which determines the di- rection of the data transfer, i.e. whether data will be written to or read from the slave device. the peripheral whose address corresponds to the trans- mitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. if the r/ w bit is a 0 then the master will write to the slave device. if the r/ w bit is a 1 the master will read from the slave de- vice. 2. data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to figure 10. writing to the address pointer register to se- lect a register for a subsequent read operation high transition when the clock is high may be inter- preted as a stop signal. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the mas- ter device will pull the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of opera- tion is determined at the beginning and cannot subse- quently be changed without starting a new operation. sda ack. by ad7994/3 start by master frame 1 serial bus address byte frame 2 address pointer register byte ack. by ad7994/3 191 9 c4 c3 c2 p2 p1 p0 r/ a0 a1 a2 a3 0 0 scl stop by master 1 c1 p3
ad7994/ad7993 ?22? rev. prf preliminary technical data figure 11. single byte write sequence figure 12. two byte write sequence reading data from the ad7994/ad7993 reading data from the ad7994/ad7993 is a one or two byte operation. reading back the contents of the configu- ration register, alert status register or the cycle timer register is a single byte read operation as shown in figure 13. this assumes the particular register address has previ- ously been set up by a single byte write operation to the address pointer register, figure 10. once the register sda ack. by ad7994/3 start by master frame 1 serial bus address byte frame 2 address pointer register byte ack. by ad7994/3 191 9 c4 c3 c2 p2 p1 p0 r/ a0 a1 a2 a3 0 0 scl 1 c1 p3 91 9 d7 d6 d5 d2 d1 d0 d4 d3 stop by master ack. by ad7994/3 frame 3 data byte scl (continued) sda (continued) sda ack. by ad7994/3 start by master frame 1 serial bus address byte frame 2 address pointer register byte ack. by ad7994/3 191 9 c4 c3 c2 p2 p1 p0 r/ a0 a1 a2 a3 0 0 scl 1 c1 p3 91 9 d7 d6 d5 d2 d1/0 d0/0 d4 d3 stop by master ack. by ad7994/3 least significant data byte scl (continued) sda (continued) 91 0 0 0 d10 d9 d8 0 d11 stop by master ack. by ad7994/3 most significant data byte address has been set up, any number of reads can subse- quently be performed from that particular register without having to write to the address pointer register again. if a read from a different register is required, then the relevant register address will have to be written to the address pointer register and again any number of reads from this register may then be performed. reading data from the conversion result register, data high registers, data low registers or hysteresis registers is a two byte operation as shown in figure 14. the same rules apply for a two byte read as a single byte read. if the master is write addressing the ad7994/ad7993 and wishes to write to more than one register, then after the first write operation has completed for the first data regis- ter in the next byte they can simply write to the address pointer byte to select the next data register for a write operation. this eliminates the need to re-address the de- vice in order to write to another data register.
ad7994/ad7993 ?23? rev. prf preliminary technical data figure 14. reading two bytes of data from the conversion result register figure 13. reading a single byte of data from a selected register device will win communication rights via standard i 2 c arbitration during the slave address transfer. the alert output becomes active when the value in the conversion result register exceeds the value in the data high register or falls below the value in the data low register . it is reset when a write operation to the configuration register sets d1 to a 1, or when the conversion result returns n lsbs below or above the value stored in the data high register or data low register respectively. n is the value in the hysteresis register. (see limit registers section) the alert output requires an external pull-up resistor. this can be connected to a voltage different from v dd provided the maximum voltage rating of the alert out- put pin is not exceeded. the value of the pull-up resistor depends on the application, but should be as large as pos- sible to avoid excessive sink currents at the alert out- put. alert/busy pin the alert/busy may be configured as an alert or busy ouput as shown in table vi. smbus alert the ad7994/ad7993 alert output is an smbus inter- rupt line for devices that want to trade their ability to master for an extra pin. the ad7994/ad7993 is a slave only device and uses the smbus alert to signal the host device that it wants to talk. the smbus alert on the ad7994/ad7993 is used as an out of conversion range indicator (a limit violation indicator). the alert pin has an open-drain configuration which allows the alert outputs of several ad7994/ad7993 devices to be wired-and together when the alert pin is active low. d0 of the configuration register is used to set the active polarity of the alert output. the power- up default is active low. the alert function can be disabled or enabled by setting d2 of the configuration register to 1 or 0 respectively. the host device can process the alert interrupt and simultaneously access all smbus alert devices through the alert response address. only the device which pulled the alert low will acknowledge the ara (alert re- sponse address). if more than one device pulls the alert pin low, the highest priority (lowest address) sda no ack. by master start by master frame 1 serial bus address byte frame 2 single data byte from ad7994/3 ack. by ad7994/3 191 9 d7 d6 d5 d2 d1 d0 r/ a0 a1 a2 a3 0 1 scl stop by master d4 d3 0 sda ack. by master start by master frame 1 serial bus address byte frame 2 most significant data byte from ad7994/3 ack. by ad7994/3 191 9 alert_ flag d10 d9 d8 r/ a0 a1 a2 a3 0 0 scl 1 d11 no ack. by master frame 3 least significant data byte from ad7994/3 19 d7 d6 d5 d2 d1/0 d0/0 stop by master d4 d3 scl (continued) sda (continued) ch id1 ch id0 0
ad7994/ad7993 ?24? rev. prf preliminary technical data placing the ad7994-1/ad7993-1 into high-speed mode. hs-mode communication commences after the master addresses all devices connected to the bus with the master code, 00001xxx, to indicate that a high-speed mode transfer is to begin. no device connected to the bus is allowed to acknowledge the high-speed master code, therefore the code is followed by a not-acknowledge, fig- figure 15. placing the part into hs mode modes of operation when supplies are first applied to the ad7994/ad7993, the adc powers up in shutdown mode and will normally remain in this shutdown state while not converting. there are three different methods of initiating a conversion on the ad7994/ad7993. mode 1 - using convst pin. a conversion can be initiated on the ad7994/ad7993 by pulsing the convst signal. the conversion clock for the part is internally generated so no external clock is required, except when reading from, or writing to the serial port. on the rising edge of convst the ad7994/ ad7993 will begin to power up, see point a on figure 16. the power up time from shutdown mode for the ad7994/ad7993 is approximately 1 us, the convst signal must remain high for 1 s for the part to power up fully. then convst can be brought low after this time. the falling edge of the convst signal places the track and hold into hold mode and a conversion is also initiated at this point, see point b figure 16. when the conversion is complete, approximately 2 us later, the part will return to shutdown (see point c figure 16) and remain so until the next rising edge of convst . the master can then read address the adc to obtain the conversion result. the address point register must be pointing to the conversion result register in order to read back the conversion result. if the convst pulse does not remain high for more than 1 s, then the falling edge of convst will still initiate a conversion but the result will be invalid as the ad7994/ad7993 will not be fully powered up when the conversion takes place. the convst pin should not be pulsed when reading from or writing to the serial port. the cycle timer register and bits c4 - c1 in the ad- dress pointer register should contain all 0?s to operate the ad7994/ad7993 in this mode. the convst pin should be tied low for all other modes of operation. to select an analog input channel for conversion in this mode, the user must write to the configuration register and select the corresponding channel for conversion. to set up a sequence of channels to be converted on with each convst pulse, set the corresponding channel bits in the configuration register, see table v. ure 15. the master must then issue a repeated start fol- lowed by the device address with a r/ w bit. the selected device will then acknowledge its address. all devices continue to operate in hs-mode until such a time as the master issues a stop condition. when the stop condition is issued the devices all return to f/s mode. figure 16. mode 1 operation 1 1 9 scl 9 s 7-bit address ra first data byte (msbs) a second data byte (lsbs) 9 p sda t convert t power-up b ac sda ack. by ad7994/3 start by master hs-mode master code serial bus address byte nack. 191 9 0 1 a2 a1 a0 x x 1 0 0 0 scl 0 0 a3 x sr fast mode high-speed mode
ad7994/ad7993 ?25? rev. prf preliminary technical data mode 2 - this mode allows a conversion to be automatically initi- ated anytime a read operation occurs. in order to use this mode the command bits c4 - c1 in the address pointer byte shown in table ii must be programmed. to select a particular analog input for conversion in this mode, then the user must set the corresponding channel command bit to 1 in the address pointer byte, see table xiii. when all four command bits are 0 then this mode is not in use. a sequence can also be set up for this mode, if more than one of the command bit in the address pointer byte are set. the adc will start converting on the lowest channel in the sequence and then the next lowest until all the channels in the sequence have been converted on. figure 13 illustrates a two byte read operation from the conversion result register. this operation would nor- mally be preceded by a write to the address pointer regis- ter so that the following read will access the desired register, in this case the conversion result register fig- ure 10. when the contents of the address pointer register are being loaded, if the command bits c4 to c1 are set then the ad7994/ad7993 will begin to power up and convert upon the selected channel(s), power-up will begin on the fifth scl falling edge of the address point byte, see point a figure 17. table xiii shows the channel se- lection in this mode via the command bits, c4 to c1 in the address pointer register. the wake-up and conversion time together should take approximately 3
ad7994/ad7993 ?26? rev. prf preliminary technical data figure 17. mode 2 operation figure 18. mode 2 sequence operation mode 3 - automatic cycle mode an automatic conversion cycle can be selected and enabled by writing a value to the cycle timer register. a conver- sion cycle interval can be set up on the ad7994/ad7993 by programming the relevant bits in the 3-bit cycle timer register as decoded in table xiib. when the cycle timer register is programmed with any configuration other than all 0?s, a conversion will take place every x ms, depending on the configuration of these bits in the cycle timer register. there are 7 different cycle time intervals to choose from as shown in table xiib. once the conver- sion has taken place the part powers down again until the next conversion occurs. to exit this mode of operation the user must program the cycle timer register to contain all 0?s. for cycle interval options see table xiib cycle timer intervals. to select a channel(s) for operation in the cycle mode set the corresponding channel bit(s), d7 to d4, of the configuration register. if more than one chan- nel bit is set in the configuration register the adc will automatically cycle through the channel sequence, start- ing with the lowest channel and working its way up through the sequence. once the sequence is complete the adc will start converting on the lowest channel again, continuing to loop through the sequence until the cycle timer register contents are set to all 0?s. this mode is useful for monitoring signals, e.g. battery voltage, tem- perature etc, interrupting only when the limits are vio- lated. 9 1 1 a scl 9 s 7-bit address wa command/address point byte a sda sr 7-bit address ra first data byte (msbs) a second data byte (lsbs) sda 1 1 9 scl 9 9 sr/ p 8 ack by ad7994/3 ack by ad7994/3 ack by ad7994/3r ack by master nack by master 9 1 1 a scl 9 s 7-bit address wa command/address point byte a sda first data byte (msbs) a second data byte (lsbs) a sr 7-bit address ra sda 9 9 1 1 scl 9 8 ack by ad7994/3 ack by ad7994/3 ack by ad7994/3 ack by master first data byte (msbs) a second data byte (lsbs) ack by master ack by master 9 9 result from ch1 result from ch2 a/
ad7994/ad7993 ?27? rev. prf preliminary technical data 16-lead tssop (ru-16) outline dimensions dimensions shown in inches and (mm). 16 9 8 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 it is recommended that no i 2 c bus activity occurs when a conversion is taking place. however if this is not possible, e.g. when operating in mode 2 or mode 3, then in order to maintain the performance of the adc, bits d7 and d6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the i 2 c bus. this will result in a quiet pe- riod for each bit decision. in certain cases where there is excessive activity on the interface lines this may have the effect of increasing the overall conversion time. however if bit trial delays extend longer than 1 s the conversion will terminate. when bits d7 and d6 are both 0, the bit trial and sample interval delaying mechanism will be implemented. the default setting of d7 and d6 is 0. to turn off both set d7 and d6 to 1. d7 d6 d5 d4 d3 d2 d1 d0 sample bit trial 0 0 0 cyc cyc cyc dealy delay bit2 bit1 bit0 0* 0* 0* 0* 0* 0* 0* 0* cycle timer register *default settings at power-up

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